Rate-compatible LDPC codes

ABSTRACT

Method and apparatus for generating codewords with variable length and redundancy from a single Low-Density Parity-Check (LDPC) code with variable length input words. A mother code for encoding data words is generated based on a parity-check matrix, wherein the mother code is adjusted to reflect the size of the data word to be encoded. A generator matrix applies the mother code to data words to produce codewords for transmission. In one embodiment, a reduction criteria is determined and the size of the generator matrix reduced in response. The corresponding parity-check matrix is applied at the receiver for decoding the received codeword.

BACKGROUND

[0001] 1. Field

[0002] The present invention relates generally to communications, andmore specifically, to rate-compatible error-correcting coding using LowDensity Parity-Check (LDPC) codes.

[0003] 2. Background

[0004] In communication systems that employ rate adaptation, forexample, wherein the transmission data rate is adjusted according toconditions and demands of the system, there is a need to transmit dataso as to flexibly and efficiently adapt the data rate to the currentchannel conditions. Typical error correcting designs, for example,select a fixed code, the code having a certain rate and correctioncapability. To add flexibility for handling different amounts of datahaving different error protection requirements, adjusting totime-varying channel conditions, as well as compensating forinsufficiently known parameters, flexible channel encoding may beemployed.

[0005] For flexible channel encoding, the data bits may be grouped intoblocks of varying size, and these blocks may be encoded with differentamounts of redundancy, resulting in codewords of different lengths.Instead of using several separate error correcting codes to encode thedifferent groups of bits, it is desirable to use a single mother codethat may accommodate several rates. This is referred to asrate-compatible coding. Using a single code instead of separate codesfor each desired rate may significantly reduce the complexity of bothencoding at the transmitter and decoding at the receiver, however, thereduced complexity is achieved at the expense of some performancedegradation. One such method for rate-compatible coding involvesRate-Compatible Punctured Convolutional (RCPC) codes. This and othercurrent methods offer limited performance or incur undesirablecomputational complexity at the decoder.

[0006] There is a need therefore, to provide high performancerate-compatible coding schemes that support rate adaptation whileminimizing the complexity of the encoder and the decoder.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 is a diagram of a coded transmission scheme in acommunication system.

[0008]FIG. 2 is a Tanner graph representation of a parity check matrixH.

[0009]FIG. 3 illustrates encoding of a data word u, by a generatormatrix G to form a codeword c.

[0010]FIG. 4 illustrates parity check of a received codeword y byapplying the parity check matrix H.

[0011]FIG. 5 illustrates a rate-compatible parity-check matrix H.

[0012]FIG. 6 illustrates a rate-compatible parity-check matrix H insystematic form.

[0013]FIG. 7 illustrates a wireless communication system employingrate-compatible coding.

[0014]FIGS. 8A and 8B are flow diagrams illustrating rate-compatibleencoding at the transmitter.

[0015]FIGS. 9A and 9B are flow diagrams illustrating adaptive decodingat the receiver.

[0016]FIG. 10 is a flow diagram illustrating encoding of data wordsincorporating generator matrix reduction.

[0017]FIG. 11 is a flow diagram illustrating decoding of code wordsincorporating parity-check matrix reduction.

[0018]FIG. 12 is a flow diagram illustrating an encoding process ofrate-compatible coding incorporating generator matrix reduction.

[0019]FIG. 13 is a flow diagram illustrating a decoding process ofrate-compatible coding incorporating parity-check matrix reduction.

DETAILED DESCRIPTION

[0020] An error correction coding system is typically designed tosatisfy a protection requirement for data transmissions. A fixed codewith a given code rate is selected. The correction capability is matchedto the protection requirement and adapted to the average or worst casechannel conditions to be expected. For rate adaptation, the codingsystem should be flexible as data for transmission may have a variety ofdifferent error protection needs. Additionally, adaptation requiresresponding to the time-varying channel conditions.

[0021]FIG. 1 illustrates a wireless communication system 100 having atransmitter 106 and receiver 110. Each of the transmitter 106 andreceiver 110 may be a transceiver capable of transmission and receipt ofdata communications. For simplicity only those functional modules usedin the following description are illustrated in system 100 of FIG. 1.The transmitter 106 includes a transmission source 102 and avariable-rate encoder 104. The transmitter 106 and receiver 110communicate via a channel 108. The receiver includes a variable-ratedecoder 112 and an information sink 114. The information to betransmitted from the source 102 may include Source Specific Information(SSI) indicating the protection requirements of the data, such ascontrol and signaling information corresponding to a data stream. Thesource 102 provides the SSI (if any) to the encoder 104. The encoder 104applies the SSI to rate adaptation, wherein, the transmission rate isadjusted in response thereto. The encoder 104 further receives ChannelState Information (CSI) that provides information as to the changingcharacteristics and quality of the channel 108. The transmitter 106 mayuse CSI to determine the coding used for a transmission. The encoder 104applies variable codes adapted to the source 102 and channel 108.

[0022] It is desirable to incorporate one encoder structure that may bemodified for rate adaptation and avoid switching between differentencoders for each rate combination. One method for providing a singleencoder structure punctures a convolutional code, wherein certain codebits are not transmitted. Such codes are referred to as Rate-CompatiblePunctured Convolutional (RCPC) codes. Note that convolutional codes arejust one example of rate-compatible codes, alternate embodiments mayincorporate other rate-compatible codes such as punctured block codes,punctured turbo codes, etc.

[0023] The punctured convolutional codes satisfy a rate-compatibilityrestriction, wherein high rate codes are embedded in lower rate codes.While RCPC coding facilitates the use of a single encoder structurethere is a degradation in performance.

[0024] According to one embodiment, the encoder 104 applies a method forgenerating codewords with variable length and redundancy from a singleLow-Density Parity-Check (LDPC) code with variable length input words.An LDPC code is a block code specified by a parity-check matrix, whichcontains mostly zeroes and only a few numbers of ones.

[0025] The communication system 100 considered may have short tomoderate block lengths. LDPC codes have demonstrated impressiveperformance, significantly better than convolutional codes andcomparable to turbo codes. Note that both turbo codes and LDPC codesincur considerable decoding complexity, but LDPC codes have thepotential to be decoded much more efficiently, and therefore faster thanturbo codes. In systems with very high data rates, such as futureWireless Local Area Networks (WLANs) or Wireless Personal Area Networks(WPANs) with data rates of 100 Mbits/s and higher, a turbo decoderintroduces a serious bottleneck to processing at the receiver 110. LDPCcodes provide an alternative for satisfying stringent requirements interms of bit error rate and decoding speed.

[0026] There are two types of LDPC codes: regular and irregular. Thedefinitions for irregular and regular LDPC codes are providedhereinbelow. It has been reported that irregular LDPC codes outperformboth regular LDPC codes and turbo codes for very long block lengths.However, for short to moderate block lengths, the performanceimprovement over the latter two codes is marginal. Regular codes, on theother hand, may be designed to have very large minimum distance d_(min)(discussed hereinbelow), which may not be the case with an irregularcode. Note that regular codes designed to have very large minimumdistances d_(min) have good error detection capability. Additionally,the structure of regular codes supports efficient parallel decoderimplementation, and therefore, very high decoding speeds can beachieved. The following discussion considers regular LDPC codesspecifically, however, alternate embodiments may apply irregular LDPCcodes.

[0027] An LDPC code is a linear error-correcting block code. The LDPCcode is specified by a sparse “parity-check” matrix H of size (n−k)×nrows by columns, where k is the size of the input block and n is thesize of the output block (codeword). The parity-check matrix H ischaracterized by its low density meaning a small number of nonzeroelements. The code rate is given by $R = {\frac{k}{n}.}$

[0028] A regular LDPC code contains t 1's per column s 1's per row,wherein s is given as:

s=t·(n|n−k),  (1)

[0029] wherein t<<(n−k), and therefore, s>t. The (n−k) rows of H arereferred to as parity checks and the elements of the LDPC codeword arereferred to as bits. The matrix H may be represented as a bipartitegraph known as the probability dependency graph or the Tanner graph withone subset of nodes representing all the bits and the other subset ofnodes representing all the parity checks. As a simplistic butillustrative example, consider a 4×8 parity-check matrix given as:$\begin{matrix}{H = \begin{bmatrix}1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 1 & 1 & 0 & 0 \\1 & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\0 & 1 & 0 & 0 & 1 & 0 & 0 & 1\end{bmatrix}} & \left( {1a} \right)\end{matrix}$

[0030] The Tanner graph representation of H consists of n=8 bit nodesand n−k=4 check nodes, as illustrated in FIG. 2. The bit nodes areidentified as the circular nodes labeled X₁, X₂, . . . , X₈ andcorrespond to the 8 coded bits of a codeword generated with this code.The check nodes are identified as the square nodes labeled f₁, f₂, f₃,f₄ and correspond to the 4 parity checks performed by H.

[0031] Decoding of LDPC codes is commonly performed using a methodreferred to as the “message-passing” algorithm. This algorithm operateson the Tanner graph representation of the parity-check matrix, andcomputes “soft” bit decisions comprising sign and reliabilityinformation for the coded bits as well as soft information about theparity checks. Messages containing soft bit decisions and messagescontaining soft parity-check information are then exchanged in aniterative manner between the bit nodes and the check nodes until apredetermined stopping criterion is reached. Final “hard” bit decisionscan then be made.

[0032] Note that in contrast to a regular LDPC code, an irregular LDPCcode has a non-uniform distribution of 1's in its rows and columns. Ineither case, the parity-check matrix has a low density of 1's. Theparity-check matrix may be constructed by appending weight-t columnvectors generated at random such that the resulting row weight is s. Inorder to reduce the probability of low-weight codewords, constrain t≧3and limit any two columns in H to only one occurrence of overlappingnon-zero bits. In other words, when arbitrarily selecting two columns inthe matrix H, the 1's in the two columns should not occur in the sameposition more than once. Else, cycles in the corresponding Tanner graphwill occur, which may cause the decoding performance to deteriorate. Theprobability of finding a “good” code, i.e., a code that has a larged_(min), with such semi-random construction, is very close to one forlarge n. The minimum distance of a code, d_(min), refers to the minimumnumber of bit errors that can occur if the decoder makes a wrongdecision. The codeword with the minimum distance from the correctcodeword is the most likely wrong decision the decoder will make, asthat decision is the nearest one to the correct one. Other wrongdecisions may occur from time to time, but it is the one with theminimum distance that usually dominates the performance. The minimumdistance is determined by the structure of an individual code. Inaddition to the method mentioned above, there are a variety of othermethods for generating parity-check matrices with the desiredproperties.

[0033] According to one embodiment, once the parity-check matrix hasbeen constructed, the matrix H is put in the form:

H=[P

I_(n−k)k]  (2)

[0034] via Gauss-Jordan elimination and, possibly, column swapping. Thematrix I_(n−k) is the identity matrix of size (n−k)×(n−k). The matrix Phas size (n−k)×k. The corresponding code generator matrix G is given as:

G=[I_(k)

P^(T)]  (3)

[0035] satisfying the property:

G·H^(T)=0.  4)

[0036] Having the generator matrix in this form yields a systematiccode, which is beneficial in one embodiment. The mapping (encoding) of adata word u into the codeword c is performed according to the equation:

c=u·G,  (5)

[0037] wherein u and c are both row vectors, wherein the generatormatrix G is used at the transmitter. The parity-check matrix is used atthe receiver to perform up to (n−k) separate parity checks on thereceived codeword y. The received codeword is given as:

y=c+e,  (6)

[0038] wherein e denotes an error word. A check is performed at thereceiver to verify that:

y·H^(T)=0,  (7)

[0039] implying that the error word is e=[0 0 . . . 0], i.e., thereceived and decoded codeword contains no errors. If (7) is notsatisfied, the decoded codeword contains errors.

[0040] The transposed parity-check matrix H^(T) is given as$\begin{matrix}{H^{T} = \begin{bmatrix}P^{T} \\\ldots \\I_{n - k}\end{bmatrix}} & (8)\end{matrix}$

[0041] The process of encoding using the generator matrix G and theprocess of decoding and then verifying the received codewords or samplesusing the parity check matrix H are illustrated in FIG. 7. The system250 includes an information source 252 which provides data to encoder204. The actual code (i.e., matrices H and G) may be generated off-lineand is not necessarily part of the encoding/decoding performed by thesystem during operation. The encoder 204 encodes the data and transmitsthe encoded data to a receiver via a transmission link 208. Decoding andparity checking are performed at unit 262, and the results provided to asink 264 for use at the receiver.

[0042] Using the (n,k) mother code, the generator matrix G may be usedto encode data words that are shorter than k into codewords with varyingcode rates to accommodate a range of desired data rates. First, considerthe encoding of a short data word of length k_(eff) wherein k_(eff)<k.FIG. 3 illustrates generation of the codeword c from the input data wordu. In this example, u includes k elements: 1) k_(eff) data elements,represented as u₀,u₁, . . . ,u_(k) _(eff) ⁻¹; and 2) (k−k_(eff)) zeroes.The generator G is then applied to the input data word u. The resultingcodeword consists of (k−k_(eff)) zeros, k_(eff) systematic bits (whichare simply the original data bits), and (n−k) parity bits. The zeros maybe discarded prior to transmission if desired, yielding a codeword oflength n_(eff), given as:

n _(eff) =n−k+k _(eff)  (9)

[0043] with the new code rate given as:

R′=k _(eff) /n _(eff)  (10)

[0044] The zero-padding is equivalent to deleting the top (k−k_(eff))rows of G (or P^(T)). In practice, the encoding of a data word of lengthk_(eff) may not involve zero-padding. Rather, it may simply involvemultiplying the k_(eff) data bits by the matrix P^(T) (minus its top(k−k_(eff)) rows) and the final codeword would consist only of theresulting (n−k) parity bits appended to the k_(eff) systematic bits. Atthe receiver, the parity-check matrix H^(T) (with the corresponding(k−k_(eff)) uppermost rows deleted) performs (n−k) separate paritychecks, as shown in FIG. 4. The zeroes are reinstated in FIG. 4 toillustrate that the received shortened codeword is a subset of themaximum-length codeword. Specifically, FIG. 4 illustrates the receivedcodeword with the (k−k_(eff)) zeros reinstated, as well as the k_(eff)systematic bits; and the (n−k) parity bits, but in practice, the paritychecks performed at the receiver may only involve the (n−k+k_(eff))systematic and parity bits as well as H^(T) (minus its (k−k_(eff))uppermost rows). The receiver verifies the received codeword y when theresult of y·H^(T) satisfies Equ. (7) given hereinabove.

[0045]FIG. 8A illustrates operation at the transmitter, wherein theprocess 300 for preparing a data word for transmission first retrievesthe appropriate generator matrix from memory at step 302. When a dataword is received at step 304 the process determines the size of the dataword. If the data word has a size k_(eff) less than k, zeroes (step 306)are added to pad the data word to generate u at step 308. The paddeddata word u is then applied to the generator matrix G.

[0046]FIG. 8B illustrates alternate processing 350 at the transmitterwherein the generator matrix G is retrieved from memory at step 352.When a data word is received at step 354 the process determines the sizeof the data word. If the data word has a size k_(eff) less than k (step356) then processing continues to step 360 to apply the data word to aportion, such as the lower portion, of the generator matrix G. In thiscase, the data word is not padded with zeroes. Else, the processingcontinues to step 358 to apply the data word to the full generatormatrix G.

[0047] At the receiver, as illustrated in FIG. 9A, a process 400 beginsby retrieving a parity-check matrix H from memory at step 402. Theparity-check matrix H corresponds to the generator matrix G of FIG. 8A.A codeword y is received at step 404, and the size of the codeworddetermined. If the length of the received codeword y is less than n(step 406) (k−k_(eff)) rows of the parity check matrix H are disregardedat step 408. The codeword y is then applied to the parity-check matrix H(minus (k−k_(eff)) rows) at step 410.

[0048]FIG. 9B illustrates alternate processing 450 at the receiverwherein the parity-check matrix H is retrieved from memory at step 452.A codeword y is received at step 454, and the size of the codeworddetermined. If the length of the received codeword y is less than n(step 456) the codeword is padded with (k−k_(eff)) zeroes at step 458 toresult in a length n. Else processing continues to step 460 to apply thefull parity-check matrix H.

[0049] Additionally, consider the encoding of a full-length data word,i.e., length k, into a codeword with fewer than (n−k) parity bits. Toreduce the number of parity bits by n_(p), the last n_(p) parity bitsmay be punctured after encoding, or it is possible to omit thecomputation of the last n_(p) parity bits entirely, which is equivalentto deleting the n_(p) rightmost columns of G (or PT) The columns to bedeleted are represented in FIG. 3 as a lightly shaded rectangle 204. Inthis case, the resulting code rate is given as:

R′=k/(n−n _(p)).  (11)

[0050] At the receiver, the corresponding parity-check matrix consistsof only the (n−k−n_(p)) leftmost columns of the original HT matrix, asillustrated in FIG. 4, wherein the retained columns are represented by adark grey shaded rectangle 202. Alternatively, the decoder may treat the“missing” parity bits as erasures and insert zeros in their place priorto performing all the (n−k) parity checks.

[0051] When using a parity-check matrix made up of a subset of thecolumns of H^(T) to obtain higher rate codewords as describedhereinabove, it is desirable that the properties of the full-sizeparity-check matrix carry over to the smaller matrix. In particular, thesmallest size parity-check matrix must satisfy the constraint that t≧3.

[0052] As an example, consider a mother code capable of generatingcodewords with four different rates. The parity-check matrix of themother code is illustrated in FIG. 5. The smallest size parity-checkmatrix is labeled as H₁, and has column weight %, i.e., it has t 1's percolumn. Additional matrices may be formed therefrom by extension at thebottom right corner. The second smallest matrix, referred to as H₂,consists of H₁ extended by a square matrix at the bottom right cornerwhose columns all have weight %, a matrix of all-zeros on the right handside and a very sparse matrix to the bottom. In the sparse submatrix,each row has at least one 1 to ensure sufficient dependencies betweenthe coded bits of the smaller and the extended matrices, but otherwiseis left very sparse to simplify both code construction and decoding. Theresulting parity-check matrix, H₂, has a column weight of at least t.Hence, it is no longer a regular parity-check matrix albeit a nearlyregular one. The larger matrices, referred to as H₃ and H₄,respectively, are constructed in the same manner. After the full-sizematrix has been constructed, it is put into systematic form usingGauss-Jordan elimination, as described previously. The resulting matrixH is illustrated in FIG. 6.

[0053]FIG. 10 illustrates a method for encoding a data word using fewerthan (n−k) parity bits. The process 500 begins by retrieving a generatormatrix G at step 502. A data word is received at step 504. In this case,a criterion is determined, such as the channel condition measured abovea threshold, at step 506. For a good channel condition there is a desireto transmit less than the full amount of parity bits. When the channelcondition is good, the size of the generator matrix G is reduced at step508 by deleting a portion of the parity columns. The data word u is thenapplied to the generator matrix G.

[0054]FIG. 11 illustrates a corresponding process 600 for decoding areceived transmission supporting the reduction of the size of aparity-check matrix wherein a parity-check matrix H is retrieved frommemory in step 602. A codeword is received at step 604. If a reductioncriterion is met at decision diamond 606, the process continues to step608 to reduce the size of the parity check matrix by disregarding n_(p)of its columns. Else, processing continues to step 610 to apply thereceived message y to the full-size parity-check matrix H. Note thatafter reduction of the parity-check matrix H at step 608, the processingalso proceeds to step 610.

[0055] Combinations of the two cases discussed above are also possible,i.e., wherein the input data word has length k_(eff)<k and only(n−k−n_(p)) parity bits are generated. In this case, only the top(n−k−n_(p)) rows of H corresponding to either H₁, H₂ or H₃ would be usedand the (k−k_(eff)) leftmost columns of H (or, equivalently, the top(k−k_(eff)) rows of H^(T)) would be deleted, as indicated by the dottedvertical line in FIG. 6. Deleting these columns does not significantlyalter the properties of the overall parity-check matrix.

[0056]FIG. 12 illustrates an encoding embodiment that combines a processas in FIG. 8A with the process as in FIG. 10. As illustrated, if thelength of the data word is less than the input block length (706) thedata word is padded with zeroes at step 708. The process then evaluatesa reduction criterion at step 710. The reduction criteria may be achannel quality criteria, such as C/I threshold(s), etc. Alternateembodiments may use other criteria that effect the operation and/orperformance of a given system. The size of the generator matrix is thenreduced (712) if the reduction criterion is satisfied.

[0057]FIG. 13 illustrates a decoding embodiment that combines a processas in FIG. 9A with a process as in FIG. 11. As illustrated, if thelength of the data word is less than the input block length (806) rowsin the parity check matrix are disregarded at step 808, and the processthen evaluates a reduction criteria at step 812. The reduction criteriamay be a channel quality criteria, such as C/I threshold(s), etc.Alternate embodiments may use other criteria that effect the operationand/or performance of a given system. The size of the parity-checkmatrix is then reduced (814) if the reduction criterion is satisfied.

[0058] As mentioned earlier, LDPC codes may, in general, be decodedusing a method referred to as the message-passing algorithm, which aimsto find the most probable codeword such that Equ. (7) is satisfied, andoperates on the graphical representation of the parity-check matrixknown as the Tanner graph. The graph consists of n bit nodes, whichrepresent the coded bits, and (n−k) check nodes, which represent the(n−k) parity checks specified by the parity-check matrix. The algorithmpasses probability messages about the coded bits back and forth betweenthe bit nodes and the check nodes in an iterative manner until all (n−k)parity checks are satisfied, thus forming the basis for soft decisionsthat consist of sign and reliability information for each of the codedbits. The soft decisions may be conveniently expressed in the form ofLog Likelihood Ratios (LLRs) in the same way as is known from turbocoding. The optimal version of the message-passing algorithm is known asthe sum-product algorithm, and both this and a low-complexityapproximation known as the min-sum algorithm, as well as any otheralgorithm based on message-passing, may, in general, be used to decodethe rate-compatible LDPC codes such as the embodiments describedhereinabove.

[0059] The transmitter provides the receiver with information regardingthe proper use of the parity-check matrix prior to the decoding process.The transmitter and receiver may negotiate to establish the structure ofthe matrices used at the transmitter and receiver for encoding anddecoding, respectively. Note that the proper use, e.g. which rows andcolumns are to be disregarded, etc., of the G and H matrices may benegotiated. Additionally, there may be difficulties in covering allpossible operating conditions with one single mother code; therefore asystem may have a set of mother codes to choose from, each of which canaccommodate a unique set of code rates. This allows for a finergranularity of available code rates and data rates. Alternatively, thematrix formats may be predetermined based on operating conditions orassumptions, such as link quality, or other metric.

[0060] Those of skill in the art would understand that information andsignals may be represented using any of a variety of differenttechnologies and techniques. For example, data, instructions, commands,information, signals, bits, symbols, and chips that may be referencedthroughout the above description may be represented by voltages,currents, electromagnetic waves, magnetic fields or particles, opticalfields or particles, or any combination thereof.

[0061] Those of skill would further appreciate that the variousillustrative logical blocks, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software, or combinationsof both. To clearly illustrate this interchangeability of hardware andsoftware, various illustrative components, blocks, modules, circuits,and steps have been described above generally in terms of theirfunctionality. Whether such functionality is implemented as hardware orsoftware depends upon the particular application and design constraintsimposed on the overall system. Skilled artisans may implement thedescribed functionality in varying ways for each particular application,but such implementation decisions should not be interpreted as causing adeparture from the scope of the present invention.

[0062] The various illustrative logical blocks, modules, and circuitsdescribed in connection with the embodiments disclosed herein may beimplemented or performed with a general purpose processor, a digitalsignal processor (DSP), an application specific integrated circuit(ASIC), a field programmable gate array (FPGA) or other programmablelogic device, discrete gate or transistor logic, discrete hardwarecomponents, or any combination thereof designed to perform the functionsdescribed herein. A general purpose processor may be a microprocessor,but in the alternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices, e.g., a combinationof a DSP and a microprocessor, a plurality of microprocessors, one ormore microprocessors in conjunction with a DSP core, or any other suchconfiguration.

[0063] The steps of a method or algorithm described in connection withthe embodiments disclosed herein may be embodied directly in hardware,in a software module executed by a processor, or in a combination of thetwo. A software module may reside in RAM memory, flash memory, ROMmemory, EPROM memory, EEPROM memory, registers, hard disk, a removabledisk, a CD-ROM, or any other form of storage medium known in the art. Anexemplary storage medium is coupled to the processor such that theprocessor can read information from, and write information to, thestorage medium. In the alternative, the storage medium may be integralto the processor. The processor and the storage medium may reside in anASIC. The ASIC may reside in a user terminal or communication systeminfrastructure element, including, but not limited to, a centralswitching office, a wired/wireless access point, a base station, etc. Inthe alternative, the processor and the storage medium may reside asdiscrete components in a user terminal or communication systeminfrastructure element, including, but not limited to, a centralswitching office, a wired/wireless access point, a base station, etc.

[0064] The previous description of the disclosed embodiments is providedto enable any person skilled in the art to make or use the presentinvention. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without departing from thespirit or scope of the invention. Thus, the present invention is notintended to be limited to the embodiments shown herein but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

What is claimed is:
 1. A method for encoding transmissions in acommunication system, comprising: determining a first code having afirst bit length; receiving a data word having a second bit length,wherein the second bit length is less than the first bit length; paddingthe data word with zeroes to extend the data word to the first bitlength; and encoding the padded data word using the first code.
 2. Themethod as in claim 1, wherein determining the first code comprises:determining a parity-check matrix; and determining a generator matrixbased on the parity-check matrix.
 3. The method as in claim 2, whereinthe parity-check matrix incorporates a Low Density Parity-Check (LDPC)code.
 4. The method as in claim 1, further comprising: discarding zeroesfrom the first codeword to form a shortened first codeword; andtransmitting the shortened first codeword.
 5. An apparatus, comprising:a data source; a code generator coupled to the data source, the codegenerator adapted for: receiving a data word having a second bit length,wherein the second bit length is less than the first bit length; paddingthe data word with zeroes to extend the data word to the first bitlength; and encoding the padded data word using a first code.
 6. Theapparatus as in claim 5, wherein the first code is a Low DensityParity-Check (LDPC) code.
 7. The apparatus as in claim 6, wherein thecode generator further adapted for: determining a parity-check matrix;and determining a generator matrix based on the parity-check matrix. 8.A method for decoding transmissions in a communication system,comprising: receiving a first code for decoding transmissions;determining a parity check matrix based on the first code, the firstcode having a first bit length; receiving a first codeword; and decodingthe first codeword using the parity-check matrix.
 9. The method as inclaim 8, wherein the first code is a Low Density Parity-Check (LDPC)code.
 10. The method as in claim 9, further comprising: determining if amatrix reduction criteria is met; and if the matrix reduction criteriais met, reducing the size of the parity-check matrix.
 11. An apparatus,comprising: a decoder; and a parity-check unit coupled to the decoderand adapted for: receiving a first code for decoding transmissions;determining a parity-check matrix based on the first code, the firstcode having a first bit length; receiving a first codeword; and decodingthe first codeword using the parity-check matrix.
 12. The apparatus asin claim 11, wherein the first code is a Low Density Parity-Check (LDPC)code.
 13. A method for encoding transmissions in a communication system,comprising: determining a generator matrix for converting a data wordinto a codeword; determining when a transmission channel condition isabove a threshold; and reducing the size of the generator matrix inresponse to the transmission channel condition.
 14. The method as inclaim 13, further comprising: determining a parity-check matrix, whereinthe determining the generator matrix further comprises: determining thegenerator matrix based on the parity-check matrix.
 15. The method as inclaim 14, wherein the parity-check matrix incorporates a Low DensityParity-Check (LDPC) code.
 16. A method for decoding transmissions in acommunication system, comprising: determining a parity-check matrix;receiving a first codeword having a corresponding first bit length; andreducing the size of the parity-check matrix in response to the firstcodeword.
 17. A method for encoding transmissions in a communicationsystem, comprising: generating a mother code comprising a plurality ofsub-codes; receiving a data word having a first bit length; selectingone of the plurality of sub-codes based on the first bit length; andencoding the data word using the selected sub-code.
 18. The method as inclaim 17, wherein generating the mother code comprises creating agenerator matrix, and wherein each sub-code is associated with a portionof the generator matrix.
 19. The method as in claim 18, whereinselecting comprises identifying a portion of the generator matrix foreach sub-code.
 20. The method as in claim 18, further comprising:generating the generator matrix as a function of a parity-check matrix.21. The method as in claim 20, wherein generating a parity-check matrixcomprises: generating a plurality of sub-matrices corresponding to thesub-codes.
 22. The method as in claim 20, further comprising: generatinga plurality of generator sub-matrices corresponding to the sub-codes asa function of the parity-check matrix; and updating the generator matrixusing the generator sub-matrices.
 23. A method for encoding datacomprising: generating a generator matrix having an input block length;receiving a data word of a first length; when the first length is lessthan the input block length, padding the data word with zeroes; if agenerator matrix reduction criteria is satisfied, reducing the size ofthe generator matrix; applying the data word to the reduced-sizegenerator matrix.
 24. The method as in claim 23, wherein the reductioncriteria is a channel quality criteria.
 25. The method as in claim 23,wherein the generator matrix includes parity columns, and whereinreducing the generator matrix comprises deleting at least a portion ofthe parity columns.
 26. A method for decoding data comprising:generating a parity-check matrix having an input block length; receivinga code word of a first length; when the first length is greater than orequal to the input block length, disregarding at least a portion of rowsin the parity-check matrix; if a parity-check matrix reduction criteriais satisfied, reducing the size of the parity-check matrix; applying thecode word to the parity-check matrix.
 27. The method as in claim 26,wherein the matrix reduction criteria is a channel quality criteria. 28.An apparatus for encoding transmissions in a communication system,comprising: means for determining a first code having a first bitlength; means for receiving a data word having a second bit length,wherein the second bit length is less than the first bit length; meansfor padding the data word with zeroes to extend the data word to thefirst bit length; and means for encoding the padded data word using thefirst code.
 29. An apparatus for decoding transmissions in acommunication system, comprising: means for receiving a first code fordecoding transmissions; means for determining a parity-check matrixbased on the first code, the first code having a first bit length; meansfor receiving a first codeword; and means for decoding the firstcodeword using the parity-check matrix.
 30. An apparatus for encodingtransmissions in a communication system, comprising: means fordetermining a generator matrix for converting a data word into acodeword; means for determining when a transmission channel condition isabove a threshold; and means for reducing the size of the generatormatrix in response to the transmission channel condition.
 31. Anapparatus for decoding transmissions in a communication system,comprising: means for determining a parity-check matrix; means forreceiving a first codeword having a corresponding first bit length; andmeans for reducing the size of the parity-check matrix in response tothe first codeword.
 32. An apparatus for encoding transmissions in acommunication system, comprising: means for generating a mother codecomprising a plurality of sub-codes; means for receiving a data wordhaving a first bit length; means for selecting one of the plurality ofsub-codes based on the first bit length; and means for encoding the dataword using the selected sub-code.